The present invention relates generally to a multi-port memory device. More particularly, the present invention is concerned with techniques which can be utilized effectively and profitably for realizing among others, three-port RAM (Random Access Memory) devices and the like which are included, for example, in digital switch integrated circuits serving as time switches in a time-sharing digital exchange.
Such a multi-port memory is known which is provided with a plurality or multiplicity of access ports including write ports and/or read ports. Further, there is also known a time-sharing digital exchange in which a digital switch integrated circuit including the multi-port memory device is used as a time switch.
The multi-port memory requires a plurality of word lines and bit lines to be provided in correspondence to the individual access ports. Consequently, as the number of the access ports increases, the layout area required for implementing the multi-port memory increases with the layout design becoming more intricate and complicated. As an approach for coping with this problem, there has already been proposed a three-port RAM device such as shown in FIG. 1 of the accompanying drawing with a view to achieving reduction of the required layout area and simplification of the layout design by implementing the read bit line by a single-ended or simplex line. More specifically, in the three-port RAM device known heretofore such as shown in FIG. 1, each of static type memory cells MC constituting a memory cell array MARY includes as a basic component a latch circuit constituted by a pair of inverters N6 and N7 cross-coupled to each other. The latch circuit has non-inverted and inverted input/output nodes which are coupled to non-inverted and inverted signal lines such as write bit lines BW0* (representing collectively a non-inverted write bit line BW0 and an inverted write bit line BW0) through a pair of write control MOSFETs (Metal Oxide Semiconductor Type Field-Effect Transistor; hereinafter, the insulated-gate field-effect transistor will collectively be referred to as MOSFET in abbreviation) Q63 and Q64 having respective gates coupled to a write word line WW0, and which are additionally coupled to read bit lines BRA0 and BRB0 through read control MOSFETs Q65 and Q66 having gates coupled to corresponding read word lines WRA0 and WRW0, respectively.
The read bit lines BRA0 and BRB0 are coupled to a power supply of the circuit via associated load circuitries or resistors R1 and R2, respectively, on one hand and coupled to input terminals of associated sense amplifiers SAA and SAB, respectively, on the other hand. The resistors R1 and R2 are imparted with such predetermined resistance values that level drop or lowering of level on the read bit line BRA0 or BRB0 falls below a logical threshold value of the sense amplifier SAA or SAB when the read control MOSFET Q65 or Q66 of the memory cell MC is turned on. In the sense amplifier SAA, the non-inverted output signal is delivered as a read data signal DRA, while from the sense amplifier SAB, the inverted output signal is delivered as a read data signal DRB. In this way, in the three-port RAM shown in FIG. 1, the read bit line is, so to say, simplexed (i.e. a single bit line is employed for each of the non-inverted output bit line and the inverted output bit line) by using the so-called single-ended sense amplifiers SAA and SAB in an effort to reduce the layout area required for implementation of the three-port RAM while simplifying the layout design.
For further particulars of the three-port RAM in which the read bit line is simplexed (or single-ended), reference may be made, for example, to JP-A-57-60586 (laid-open on Apr. 12, 1982).